CoWoS Capacity Limited, Reports Say TSMC Developing Semiconductor Packaging Solution Similar to Intel's EMIB
Due to limited CoWoS capacity, TSMC is developing a packaging solution similar to Intel's EMIB. The solution aims to simplify processes and reduce costs to alleviate packaging bottlenecks for AI compute chips.
CoWoS packaging technology is currently a core manufacturing link for high-end AI training and inference chips, and its capacity directly determines the chip shipment volumes of vendors such as NVIDIA and AMD. TSMC faces severe capacity bottlenecks and is therefore seeking technological breakthroughs to maintain its competitive advantage.
The "quasi-EMIB" solution being advanced internally by TSMC borrows from the flexibility of Intel's EMIB technology. Compared to traditional CoWoS processes, the new solution is expected to significantly simplify manufacturing steps and shorten production cycles, thereby effectively reducing overall packaging costs.
This technological development is significant for the AI compute supply chain. If the new solution matures and enters mass production, it will help alleviate the current situation where supply falls short of demand for AI chips, accelerating the deployment of large model training and inference infrastructure.
Intel's EMIB packaging solution has previously attracted global customers due to its flexibility. TSMC's move aims to maintain a leading position in the advanced packaging field through differentiated packaging technology, addressing the growing demand for AI compute power.
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