European Openchip Releases BER10 Processor: RISC-V Instruction Set, Sub-2nm GAA Process

European chip company Openchip has officially announced the BER10 processor. The product is designed based on the RISC-V instruction set and adopts sub-2nm GAA process technology. After 2.5 years of development, the BER10 is positioned as an industrial-grade chip capable of running actual workloads.

In terms of technical specifications, the BER10 is equipped with 4 high-performance 64-bit out-of-order cores and a wide vector processing unit. It supports multi-channel memory and PCIe connections, and is compatible with the Linux operating system. These features provide it with the basic capability to handle complex computing tasks.

Openchip has defined itself as an energy-efficient AI and HPC chip company and revealed that it will subsequently develop RISC-V computing accelerators specifically designed for data center-scale supercomputing and artificial intelligence. This indicates that the company is shifting its technical focus towards the AI computing power sector.

With the surge in computing power demand driven by AI large models, AI chips based on the RISC-V architecture have become a focus of industry attention. Openchip's layout reflects the potential application value of open-source instruction sets in the fields of high-performance computing and artificial intelligence hardware.

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